定价： 441元

定价： 574元

定价： 664元

定价： 619元

定价： 441元

定价： 307元

定价： 398元

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定价： 398元

This standard defines how the necessary information is passed from scan insertion to pattern generation and from pattern generation to diagnosis such that different tool vendors could be used for each step independent of on-chip scan compression logic used.

定价： 135元 / 折扣价： 115 元

SBus is a high performance computer I/O interface for connecting integrated circuits and SBus Cards to a computer system motherreboard. This standard defines the mechanical, electrical, environmental, and protocol requirements for the design of SBus Cards and the computer system motherreboard that supports those cards. Every SBus Card shall implement appropriate self-descriptive and initialization firmware using FCode, which is similar to the Forth programming language. The details of this… read more firmware standard are beyond the scope of IEEE Std 1496-1993. The currently active IEEE working group, P1275, will define this firmware interface standard (see IEEE P1275). In addition, other software interfaces may be used for communication with SBus Cards. read less

定价： 106元 / 折扣价： 91 元

This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from on-chip test structures. The standard re-uses existing high speed I/O (HSIO) known in the industry for the high speed test access port (HSTAP). The HSIO connects to an on-chip distribution architecture through a common interface. The scope includes the distribution architecture test logic and packet decoder logic. The objective of the distribution architecture and packet decoder is that it can be readily re-used with different integrated circuits (ICs) that host different HSIO technology, such that the standard addresses as large a part of the industry as possible. The scope includes IEEE 1149.1 Boundary-Scan Description Language (BSDL) and Procedural Description Language (PDL) documentation, which can be used for configuring a mission mode HSIO to a test mode compatible with the HSTAP. The same BSDL and PDL can then be used to deliver high-speed data to the on-chip test structures.

定价： 104元 / 折扣价： 89 元