定价： 97元 / 折扣价： 83 元

This standard defines SystemC as an ANSI standard C++ class library for system and hardware design.

定价： 407元 / 折扣价： 346 元

This recommended practice identifies digital rights (DR) requirements for eLearning technologies. These requirements should be aligned with the most widely known standards-based specifications for Digital Rights Expression Language (DREL) that are being adopted or developed by international, regional, national, and private organizations and consortia.

定价： 111元 / 折扣价： 95 元

定价： 541元 / 折扣价： 460 元

This standard defines the IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is built on IEEE Std 1076-2002 (VHDL) and extends it with additions and changes to provide capabilities of writing and simulating analog and mixed-signal models.

定价： 398元 / 折扣价： 339 元

定价： 437元 / 折扣价： 372 元

This standard defines the syntax and semantics of the VHSIC Hardware Description Language (VHDL). The acronym VHSIC (Very High Speed Integrated Circuits) in the language's name comes from the U.S. government program that funded early work on the standard.

定价： 275元 / 折扣价： 234 元

The body of the standard describes the modeling language (syntax and semantics) that supports the IDEF0 method for developing graphical representations of a system or subject area. The clauses that follow govern the physical construction of IDEF0 models that represent functions, functional relationships, and the physical and data objects required by those relationships. This part of the document is divided into 10 clauses. Clause 1 provides an overview of this part of the standard. Clause 2… read more defines key terms. Clause 3 discusses the concept of an IDEF0 model. Clause 4 defines the syntax of the IDEF0 language. Clause 5 defines the semantics of the language. Clause 6 describes the different types of IDEF0 diagrams. Clause 7 presents the different types of IDEF0 model pages. Clause 8 provides details on the various features of an IDEF0 diagram. Clause 9 defines IDEF0 reference expressions. Finally, Clause 10 defines IDEF0 diagram feature references. Documentation of best commercial practices and guides to recommended usage are beyond the scope of this document. read less

定价： 292元 / 折扣价： 249 元

This standard defines the IEEE 1076.1(TM) language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. Informally called VHDL-AMS, (VHSIC Hardware Description Language for Analog and Mixed-Signal, where VHSIC stands for Very High Speed Integrated Circuits), the language is built on the IEEE 1076(TM)(VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

定价： 274元 / 折扣价： 233 元

定价： 407元 / 折扣价： 346 元

The semantics and syntax of IDEF1X, a language used to represent a conceptual schema, are described. Two styles of IDEF1X model are described. 1. The key style is used to produce information models that represent the structure and semantics of data within an enterprise and is backward-compatible with the US government's Federal Information Processing Standard (FIPS) PUB 184, Integration Definition for Information Modeling (IDEF1X). 2. The identity style is used to produce object models that… read more represent the knowledge, behaviour, and rules of the concepts within an enterprise. It can be used as a growth path for key-style models. The identity style can, with suitable automation support, be used to develop a model that is an executable prototype of the target object-oriented system.. read less

定价： 332元 / 折扣价： 283 元