【国外标准】 IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments

Define structures in STIL to support usage as semiconductor simulation stimulus; including: 1) mapping signal names to equivalent design references, 2) interface between Scan and BIST, and the logic simulation, 3) data types to represent unresolved states in a pattern, 4) parallel or asynchronous pattern execution on different design blocks, and 5) expression-based conditional execution of pattern constructs. Define structures in STIL to support the definition of test patterns for sub-blocks of… read more a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher-level device test. Define structures in STIL to relate fail information from device testing environments back to original stimulus and design data elements. read less