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IEEE 1149.10-2017 IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture

【国外标准】 IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture

本网站发布时间： 2025-04-28

IEEE 1149.10-2017
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标准简介

适用范围：

This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from on-chip test structures. The standard re-uses existing high speed I/O (HSIO) known in the industry for the high speed test access port (HSTAP). The HSIO connects to an on-chip distribution architecture through a common interface. The scope includes the distribution architecture test logic and packet decoder logic. The objective of the distribution architecture and packet decoder is that it can be readily re-used with different integrated circuits (ICs) that host different HSIO technology, such that the standard addresses as large a part of the industry as possible. The scope includes IEEE 1149.1 Boundary-Scan Description Language (BSDL) and Procedural Description Language (PDL) documentation, which can be used for configuring a mission mode HSIO to a test mode compatible with the HSTAP. The same BSDL and PDL can then be used to deliver high-speed data to the on-chip test structures.

基本信息

标准号：
IEEE 1149.10-2017
标准名称：
IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture
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