【国外标准】 Information technology - RapidIO(TM) Interconnect Specification (version 1.3)

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interconnect, allowing chip-to-chip and board-to- board communications at Gigabyte per second performance levels.