【国外标准】 IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct… read more programming interface (DPI). Throughout this standard, the following terms apply: — Verilog refers to IEEE Std 1364 for the Verilog HDL. — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL. — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL. — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard. SystemVerilog adds extended and new constructs to Verilog, including the following: — Extensions to data types for better encapsulation and compactness of code and for tighter specification — C data types: int, typedef, struct, union, enum — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from deallocation issues — Dynamic casting and bit-stream casting — Automatic/static specification on a per-variable-instance basis — Extended operators for concise description — Wild equality and inequality — Built-in methods to extend the language — Operator overloading — Streaming operators — Set membership — Extended procedural statements — Pattern matching on selection statements for use with tagged unions — Enhanced loop statements plus the foreach statement — C-like jump statements: return, break, continue — final blocks that execute at the end of simulation (inverse of initial) — Extended event control and sequence events — Enhanced process control — Extensions to always blocks to include synthesis consistent simulation semantics — Extensions to fork…join to model pipelines and for enhanced process control — Fine-grain process control — Enhanced tasks and functions — C-like void functions — Pass by reference — Default arguments — Argument binding by name — Optional arguments — Import/export functions for DPI — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities — Automated testbench support with random constraints — Interprocess communication synchronization — Semaphores — Mailboxes — Event extensions, event variables, and event sequencing — Clarification and extension of the scheduling semantics — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development, ease maintainability, and promote reusability — Cycle-based signal drives and samples — Synchronous samples read less