【国外标准】 IEC 62526 Ed. 1 (IEEE Std 1450.1(TM)-2005): Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments

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IEEE/IEC 62526-2007
定价： 160元 / 折扣价： 136 元
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Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test (BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution of pattern constructs. Structures are defined in STIL to support the definition… read more of test patterns for sub-blocks of a design4 (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test. Structures are defined in STIL to relate fail information from device testing environments back to original stimulus and design data elements. 4 Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O. read less

基本信息

标准号：
IEEE/IEC 62526-2007
标准名称：
IEC 62526 Ed. 1 (IEEE Std 1450.1(TM)-2005): Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments
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