定价： 481元 / 折扣价： 409 元 加购物车

定价： 819元 / 折扣价： 697 元 加购物车

定价： 345元 / 折扣价： 294 元 加购物车

4.1 Solid-state electronic devices subjected to stresses from excessive current pulses sometimes fail because a portion of the metallization fuses or vaporizes (suffers burnout). Burnout susceptibility can vary significantly from component to component on a given wafer, regardless of design. This practice provides a procedure for establishing the limits of pulse current overstress within which the metallization of a given device should survive.4.2 This practice can be used as a destructive test in a lot-sampling program to determine the boundaries of the safe operating region having desired survival probabilities and statistical confidence levels when appropriate sample quantities and statistical analyses are used.Note 2—The practice may be extended to infer the survivability of untested metallization adjacent to the specimen metallization on a semiconductor die or wafer if care is taken that appropriate similarities exist in the design and fabrication variables.1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.Note 1—In this practice, “metallization” refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term “burnout” refers to either fusing or vaporization.1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.1.4 This practice is not intended to determine the nature of any defect causing failure.1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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4.1 Electronic circuits used in many space, military and nuclear power systems may be exposed to various levels of ionizing radiation dose. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems.4.2 Manufacturers are currently selling semiconductor parts with guaranteed hardness ratings, and the military specification system is being expanded to cover hardness specification for parts. Therefore test methods and guides are required to standardize qualification testing.4.3 Use of low energy (≈10 keV) X-ray sources has been examined as an alternative to cobalt-60 for the ionizing radiation effects testing of microelectronic devices (3, 4, 5, 6). The goal of this guide is to provide background information and guidance for such use where appropriate.NOTE 3: Cobalt-60—The most commonly used source of ionizing radiation for ionizing radiation (“total dose”) testing is cobalt-60. Gamma rays with energies of 1.17 and 1.33 MeV are the primary ionizing radiation emitted by cobalt-60. In exposures using cobalt-60 sources, test specimens must be enclosed in a lead-aluminum container to minimize dose-enhancement effects caused by low-energy scattered radiation (unless it has been demonstrated that these effects are negligible). For this lead-aluminum container, a minimum of 1.5 mm of lead surrounding an inner shield of 0.7 to 1.0 mm of aluminum is required. (See 8.2.2.2 and Practice E1249.)4.4 The X-ray tester has proven to be a useful ionizing radiation effects testing tool because:4.4.1 It offers a relatively high dose rate, in comparison to most cobalt-60 sources, thus offering reduced testing time.4.4.2 The radiation is of sufficiently low energy that it can be readily collimated. As a result, it is possible to irradiate a single device on a wafer.4.4.3 Radiation safety issues are more easily managed with an X-ray irradiator than with a cobalt-60 source. This is due both to the relatively low energy of the photons and due to the fact that the X-ray source can easily be turned off.4.4.4 X-ray facilities are frequently less costly than comparable cobalt-60 facilities.4.5 The principal radiation-induced effects discussed in this guide (energy deposition, absorbed-dose enhancement, electron-hole recombination) (see Appendix X1) will remain approximately the same when process changes are made to improve the performance of ionizing radiation hardness of a part that is being produced. This is the case as long as the thicknesses and compositions of the device layers are substantially unchanged. As a result of this insensitivity to process variables, a 10-keV X-ray tester is expected to be an excellent apparatus for process improvement and control.4.6 Several published reports have indicated success in intercomparing X-ray and cobalt-60 gamma irradiations using corrections for dose enhancement and for electron-hole recombination. Other reports have indicated that the present understanding of the physical effects is not adequate to explain experimental results. As a result, it is not fully certain that the differences between the effects of X-ray and cobalt-60 gamma irradiation are adequately understood at this time. (See 8.2.1 and Appendix X2.) Because of this possible failure of understanding of the photon energy dependence of radiation effects, if a 10-keV X-ray tester is to be used for qualification testing or lot acceptance testing, it is recommended that such tests should be supported by cross checking with cobalt-60 gamma irradiations. For additional information on such comparison, see X2.2.4.4.7 Because of the limited penetration of 10-keV photons, ionizing radiation effects testing must normally be performed on unpackaged devices (for example, at wafer level) or on delidded devices.1.1 This guide covers recommended procedures for the use of X-ray testers (that is, sources with a photon spectrum having ≈10 keV mean photon energy and ≈50 keV maximum energy) in testing semiconductor discrete devices and integrated circuits for effects from ionizing radiation.1.2 The X-ray tester may be appropriate for investigating the susceptibility of wafer level or delidded microelectronic devices to ionizing radiation effects. It is not appropriate for investigating other radiation-induced effects such as single-event effects (SEE) or effects due to displacement damage.1.3 This guide focuses on radiation effects in metal oxide semiconductor (MOS) circuit elements, either designed (as in MOS transistors) or parasitic (as in parasitic MOS elements in bipolar transistors).1.4 Information is given about appropriate comparison of ionizing radiation hardness results obtained with an X-ray tester to those results obtained with cobalt-60 gamma irradiation. Several differences in radiation-induced effects caused by differences in the photon energies of the X-ray and cobalt-60 gamma sources are evaluated. Quantitative estimates of the magnitude of these differences in effects, and other factors that should be considered in setting up test protocols, are presented.1.5 If a 10-keV X-ray tester is to be used for qualification testing or lot acceptance testing, it is recommended that such tests be supported by cross checking with cobalt-60 gamma irradiations.1.6 Comparisons of ionizing radiation hardness results obtained with an X-ray tester with results obtained with a LINAC, with protons, etc. are outside the scope of this guide.1.7 Current understanding of the differences between the physical effects caused by X-ray and cobalt-60 gamma irradiations is used to provide an estimate of the ratio (number-of-holes-cobalt-60)/(number-of-holes-X-ray). Several cases are defined where the differences in the effects caused by X-rays and cobalt-60 gammas are expected to be small. Other cases where the differences could potentially be as great as a factor of four are described.1.8 It should be recognized that neither X-ray testers nor cobalt-60 gamma sources will provide, in general, an accurate simulation of a specified system radiation environment. The use of either test source will require extrapolation to the effects to be expected from the specified radiation environment. In this guide, we discuss the differences between X-ray tester and cobalt-60 gamma effects. This discussion should be useful as background to the problem of extrapolation to effects expected from a different radiation environment. However, the process of extrapolation to the expected real environment is treated elsewhere (1, 2).21.9 The time scale of an X-ray irradiation and measurement may be much different than the irradiation time in the expected device application. Information on time-dependent effects is given.1.10 Possible lateral spreading of the collimated X-ray beam beyond the desired irradiated region on a wafer is also discussed.1.11 Information is given about recommended experimental methodology, dosimetry, and data interpretation.1.12 Radiation testing of semiconductor devices may produce severe degradation of the electrical parameters of irradiated devices and should therefore be considered a destructive test.1.13 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.1.14 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.1.15 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

定价： 646元 / 折扣价： 550 元 加购物车

This specification covers round drawn/extruded gold wires for internal semiconductor device electrical connections. The wires are available in four classifications, namely: copper-modified wire, beryllium-modified wire, high-strength wire, and special purpose wire. Aptly sampled wires shall be examined by test methods suggested herein, and each class shall conform correspondingly to specified requirements for chemical composition, mechanical properties (breaking load and elongation), dimension (diameter and weight), and workmanship and finish. The wires shall also undergo wire curl, wire axial twist, and wire roundness tests.1.1 This specification covers round drawn/extruded gold wire for internal semiconductor device electrical connections. Four classifications of wire are distinguished, (1) copper-modified wire, (2) beryllium-modified wire, (3) high-strength wire, and (4) special purpose wire.NOTE 1: Trace metallic elements have a significant effect upon the mechanical properties and thermal stability of high-purity gold wire. It is customary in manufacturing to add controlled amounts of selected impurities to gold to modify or stabilize bonding wire properties, or both. This practice is known variously as “modifying,” “stabilizing,” or “doping.” The first two wire classifications denoted in this specification refer to wire made with either of two particular modifiers, copper or beryllium, in general use. In the third and fourth wire classifications, “high-strength” and “special purpose” wire, the identity of modifying additives is not restricted.1.2 The values stated in SI units are to be regarded as standard. The values given in parentheses after SI units are provided for information only and are not considered standard.1.3 The following hazard caveat pertains only to the test method portion, Section 9, of this specification. This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

定价： 0元 / 折扣价： 0 元

5.1 Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of survivability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1),2 but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

定价： 590元 / 折扣价： 502 元 加购物车

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4.1 This guide is intended to help analysts in the semiconductor industry. Examples of the usefulness of anion monitoring include: (1) determining when ion-exchange resin beds (in water-purification systems) need to be regenerated, and (2) ensuring that anion levels are low enough to allow the water to be used for the manufacture of semiconductor devices.4.2 To ensure that the anions are indeed at low-ppt levels, it is recommended to check the conductivity of a subsample before proceeding with Section 5 of this guide. This check does not need to be exact; its purpose is simply to let the analyst know if the conductivity is higher than that of the highest-level standard solution being tested. Any high reading signifies that the sample, if analyzed, might contaminate the instrument.1.1 This guide applies to ultrapure water that is thought to contain low ppt (parts-per-trillion, weight/weight) levels of anionic contaminants (for example, bromide, chloride, fluoride, nitrate, nitrite, phosphate, and sulfate). To minimize carry-over problems between analyses, it is best to limit the concentration of any one contaminant to approximately 200 ppt (although this limit is only an approximation and may vary, depending on the user’s application).1.2 This guide is intended to help analysts avoid contamination of ultrapure-water samples, since contamination control is the primary challenge when quantifying ppt-level anions in grab samples.1.3 This guide does not include recommendations for collecting samples from the water source.1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.1.5 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

定价： 515元 / 折扣价： 438 元 加购物车

Update #2 was published as notification that this is now a National Standard of Canada This PDF includes Update #2 and #3 1 General NOTE - This Part is intended to be read together with the Standard for Low-Voltage Fuses - Part 1: General Require

定价： 1775元 / 折扣价： 1509 元

5.1 Many modern integrated circuits, power transistors, and other devices experience SEP when exposed to cosmic rays in interplanetary space, in satellite orbits or during a short passage through trapped radiation belts. It is essential to be able to predict the SEP rate for a specific environment in order to establish proper techniques to counter the effects of such upsets in proposed systems. As the technology moves toward higher density ICs, the problem is likely to become even more acute.5.2 This guide is intended to assist experimenters in performing ground tests to yield data enabling SEP predictions to be made.1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z ≥ 2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via another mechanism. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (persistent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor, (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read only memory, (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transistors may be tested by the procedure called out in Method 1080 of MIL STD 750.1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions, and solar flares. The techniques do not, however, simulate heavy ion beam effects proposed for military programs. The end product of the test is a plot of the SEP cross section (the number of upsets per unit fluence) as a function of ion LET (linear energy transfer or ionization deposited along the ion's path through the semiconductor). This data can be combined with the system's heavy ion environment to estimate a system upset rate.1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered.1.4 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.1.6 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

定价： 646元 / 折扣价： 550 元 加购物车

1.1 This test method covers the determination of the apparent density of ceramic parts, used in electron device and semiconductor applications, with a maximum dimension of 25 mm (1 in.) and having zero or discontinuous porosity. 1.2 The values stated in SI units are to be regarded as the standard. The values in parentheses are for information only. 1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability or regulatory limitations prior to use.

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4.1 This guide recommends the water quality required for the electronics and microelectronics industries. High-purity water is required to prevent contamination of products during manufacture, since contamination can lead to an unacceptable, low yield of electronic devices.4.2 The range of water purity is defined in accordance with the manufacturing process. The types of ultra-pure water are defined with respect to device line width. In all cases, the water-quality recommendations apply at the point of distribution.4.3 The limits on the impurities are related to current contamination specifications and to available analytical methods (either performed in a suitable clean laboratory or by on-line instrumentation). On-line and off-line methods are used in accordance with current industry practice. Concentration of the sample may be required to measure the impurities at the levels indicated in Table 1.(A) The user should be advised that analytical data often are instrument dependent and technique dependent. Thus, the numbers in Table 1 are only guidelines. This table will be revised whenever the semiconductor industry develops new linewidths, thereby keeping the guidelines current.(B) Values shown in Type E-1.3 are a result of aligning ITRS risk factors of known contaminates to the production processes found in current semiconductor processing for the linewidth of interest and may differ in a few cases to those found in Type E-1.2. Users who wish to use the higher numbers for Type E-1.2 water should feel free to do so.All values are equal to or less than with the exception of Resistivity.(C) Boron is monitored only as an operational parameter for monitoring the ion-exchange beds.1.1 This guide provides recommendations for water quality related to electronics and semiconductor-industry manufacturing. Seven classifications of water are described, including water for line widths as low as 0.032 μm. In all cases, the recommendations are for water at the point of distribution (POD).1.2 Water is used for washing and rinsing of semiconductor components during manufacture. Water is also used for cleaning and etching operations, making steam for oxidation of silicon surfaces, preparing photomasks, and depositing luminescent materials. Other applications are in the development and fabrication of solid-state devices, thin-film devices, communication lasers, light-emitting diodes, photo-detectors, printed circuits, memory devices, vacuum-tube devices, or electrolytic devices.1.3 Users needing water qualities different from those described here should consult other water standards, such as Specification D1193 and Guide D5196.1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.1.5 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

定价： 590元 / 折扣价： 502 元 加购物车

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This specification covers aluminum-1 % silicon alloy wire for semiconductor devices lead-bonding and is limited to wire of diameter up to and including 0.0020 in. (0.051 mm). The wire surface shall be clean and free of finger oils, lubricant residues, stains, and particulate matter. The elongation and breaking load shall be tested to meet the requirements prescribed. The methods in determining the wire dimensions are presented in details. Verify that the chemical requirements are satisfied by means of spectrographic analysis.1.1 This specification covers aluminum–1 % silicon alloy wire for internal connections in semiconductor devices and is limited to wire of diameter up to and including 76 μm (0.003 in.). For diameters larger than 76 μm (0.003 in.), the specifications are to be agreed upon between the purchaser and the supplier.1.2 The values stated in SI units are to be regarded as the standard, regardless of whether they appear first or second in a table. Values given in parentheses are for information only.1.3 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.

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