This standard defines a test description language that: a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment (ATE) environments; b) Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT); c) Supports the volume of test vector data generated from structured tests such as scan/automatic test pattern generation (ATPG), integral test techniques… read more such as built-in self test (BIST), and functional test specifications for IC designs and their assemblies, in a format optimized for application in ATE environments. In setting the scope for any standard, some issues are defined to not be pertinent to the initial project. The following is a partial list of issues that were dropped from the scope of this initial project: — Levels: A key aspect of a digital test program is the ability to establish voltage and current parameters (levels) for signals under test. Level handling is not explicitly defined in the current standard, as this information is both compact (not presenting a transportation issue) and commonly established independently of digital test data, requiring different support mechanisms outside the current scope of this standard. Termination values may affect levels. — Diagnostic/fault-tracing information: The goal of this standard is to optimally present data that needs to be moved onto ATE. While diagnostic data, fault identification data, and macro/design element correspondence data can fall into this category (and is often fairly large), this standard is also focused on integrated circuit and assemblies test, and most debug/failure analysis occurs separately from the ATE for these structures. Note that return of failure information (for off-ATE analysis) is also not part of the standard as currently defined. — Datalogging mechanisms, formatting, and control usually are not defined as part of this current standard. — Parametric tests are not defined as an integral part of this standard, except for optional pattern labels that identify potential locations for parametric tests, such as IDDQ tests or alternating current (AC) timing tests. — Program flow: Test sequencing and ordering are not defined as part of the current standard except as necessary to define collections of digital patterns meant to execute as a unit. — Binning constructs are not part of the current standard. — Analog or mixed-signal test: While this is an area of concern for many participants, at this point transfer of analog test data does not contribute to the same transportation issue seen with digital data. — Algorithmic pattern constructs (such as sequences commonly used for memory test) are not currently defined as part of the standard. — Parallel test/multisite test constructs are not an integral part of the current environment. — User input and user control/options are not part of the current standard. — Characterization tools, such as shmoo plots, are not defined as part of the current standard. read less

定价： 381元 / 折扣价： 324 元

Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test (BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution of pattern constructs. Structures are defined in STIL to support the definition… read more of test patterns for sub-blocks of a design4 (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test. Structures are defined in STIL to relate fail information from device testing environments back to original stimulus and design data elements. 4 Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O. read less

定价： 160元 / 折扣价： 136 元

定价： 191元 / 折扣价： 163 元

This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct… read more programming interface (DPI). Throughout this standard, the following terms apply: — Verilog refers to IEEE Std 1364 for the Verilog HDL. — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL. — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL. — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard. SystemVerilog adds extended and new constructs to Verilog, including the following: — Extensions to data types for better encapsulation and compactness of code and for tighter specification — C data types: int, typedef, struct, union, enum — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from deallocation issues — Dynamic casting and bit-stream casting — Automatic/static specification on a per-variable-instance basis — Extended operators for concise description — Wild equality and inequality — Built-in methods to extend the language — Operator overloading — Streaming operators — Set membership — Extended procedural statements — Pattern matching on selection statements for use with tagged unions — Enhanced loop statements plus the foreach statement — C-like jump statements: return, break, continue — final blocks that execute at the end of simulation (inverse of initial) — Extended event control and sequence events — Enhanced process control — Extensions to always blocks to include synthesis consistent simulation semantics — Extensions to fork…join to model pipelines and for enhanced process control — Fine-grain process control — Enhanced tasks and functions — C-like void functions — Pass by reference — Default arguments — Argument binding by name — Optional arguments — Import/export functions for DPI — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities — Automated testbench support with random constraints — Interprocess communication synchronization — Semaphores — Mailboxes — Event extensions, event variables, and event sequencing — Clarification and extension of the scheduling semantics — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development, ease maintainability, and promote reusability — Cycle-based signal drives and samples — Synchronous samples read less

定价： 449元 / 折扣价： 382 元

This recommended practice defines the processes and procedures that should be followed to implement Verification, Validation, and Accreditation (VV&A) for federations being developed using the High Level Architecture (HLA) Federation Development and Execution Process (FEDEP). This recommended practice is not intended to replace existing VV&A policies, procedures, and guidance, but rather is intended to focus on the unique aspects of the VV&A of federations. It provides a higher-… read more level framework into which such practices can be integrated and tailored for specific uses. The VV&A overlay provides implementation-level guidance to VV&A practitioners; however, it does not describe the individual techniques that might be employed to execute the VV&A processes for federations. This VV&A overlay focuses upon the VV&A processes that apply to federations and not the VV&A processes associated with individual simulations (federates), but does consider using the information produced by those processes. Users, developers, and VV&A personnel working with simulations and simulation compositions not based upon the HLA and the FEDEP can also benefit from the guidance in this document since the activities that this overlay describes can be tailored to support any type of distributed simulation application. read less

定价： 110元 / 折扣价： 94 元

This standard defines elements and commonly used components in excitation control systems and contains definitions for excitation systems as applied to synchronous machines. These definitions should be useful in the following areas: -- Writing excitation systems specifications -- Evaluating excitation system performance -- Specifying methods for excitation system tests -- Preparing related excitation system standards -- Serving as an educational means for those becoming acquainted with… read more excitation systems -- Modeling excitation systems read less

定价： 110元 / 折扣价： 94 元

This standard applies to, and provides the basis for, the definition, specification, performance analysis, and application of SCADA and automation systems in electric substations, including those associated with generating stations and power utilization and conversion facilities.

定价： 173元 / 折扣价： 148 元

IEEE Std 1500 has developed a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality of the IC or its individual embedded cores. The method creates the necessary requirements for the test of such ICs, while allowing for ease of interoperability of cores that may have originated from different sources.

定价： 357元 / 折扣价： 304 元

Electrical insulation systems and materials may be tested using constant stress tests in which times to breakdown are measured for a number of test specimens, and progressive stress tests in which breakdown voltages may be measured. In either case, it will be found that a different result is obtained for each specimen and that, for given test conditions, the data obtained may be represented by a statistical distribution. This guide describes, with examples, statistical methods to analyze such data. The purpose of this guide is to define statistical methods to analyze times to breakdown and breakdown voltage data obtained from electrical testing of solid insulating materials, for purposes including characterization of the system, comparison with another insulator system, and prediction of the probability of breakdown at given times or voltages. Methods are given for analyzing complete data sets and also censored data sets in which not all the specimens broke down. The guide includes methods, with examples, for determining whether the data is a good fit to the distribution, graphical and computer-based techniques for estimating the most likely parameters of the distribution, computer-based techniques for estimating statistical confidence intervals, and techniques for comparing data sets and some case studies. The methods of analysis are fully described for the Weibull distribution. Some methods are also presented for the Gumbel and lognormal distributions. All the examples of computer-based techniques used in this guide may be downloaded from the following web site "http:// grouper.ieee.org/groups/930/IEEEGuide.xls." Methods to ascertain the short time withstand voltage or operating voltage of an insulation system are not presented in this guide. Mathematical techniques contained in this guide may not apply directly to the estimation of equipment life.

定价： 220元 / 折扣价： 187 元

2007 NESC bundled with 2007 NESC Special Edition VuSpec CD-ROM: 2007 NESC: This standard covers basic provisions for safeguarding of persons from hazards arising from the installation, operation, or maintenance of 1) conductors and equipment in electric supply stations, and 2) overhead and underground electric supply and communication lines. It also includes work rules for the construction, maintenance, and operation of electric supply and communication lines and equipment. The standard is… read more applicable to the systems and equipment operated by utilities, or similar systems and equipment, of an industrial establishment or complex under the control of qualified persons. This standard consists of the introduction, definitions, grounding rules, list of referenced and bibliographic documents, and Parts 1, 2, 3, and 4 of the 2007 Edition of the National Electrical Safety Code. 2007 NESC VuSpec CD-ROM: You get the complete 2007 NESC in a new point-and-click HTML format as well as the official 2007 NESC in the Classic Adobe PDF format. With internet access, you get exclusive hyperlinks to essential resources including the IEEE Electrical Safety Resource Center, the NESC Zone, and so much more. New search, linking, and navigational features are available to assist you! No more thumbing through hundreds of pages for cross-referenced material. Just click! Rules are linked together enabling you to move forward and back as you like. Jump to any table in feet or meters with ease. View color-coded changes from the 2002 NESC, copy and paste an important passage, print pages on your inkjet or laser printer. Not satisfied with the size or color of the text Change it. VuSpec is customizable. Starts immediately, no installation or login required. Also includes the NESC Glossary, just key in a term and see its definition. read less

定价： 0元 / 折扣价： 0 元

This Standard defines a data model for describing, referencing, and sharing competency definitions, primarily in the context of online and distributed learning. This Standard provides a way to represent formally the key characteristics of a competency, independently of its use in any particular context. It enables interoperability among learning systems that deal with competency information by providing a means for them to refer to common definitions with common meanings. This Standard enables… read more information about competencies to be encoded and shared. This Standard does not define whether a competency is a skill, knowledge, ability, attitude, or learning outcome, but it can be used to capture information about any of these. Policies regarding reusable competency definitions (RCDs), such as the best practice to look for an existing definition to reuse instead of inventing a new one for the same purpose, are outside of the scope of this Standard. read less

定价： 134元 / 折扣价： 114 元

A Hands-on Guide to the 2007 NESC that Clarifies Code Rules for You to Achieve Full Compliance! McGraw-Hill's National Electrical Safety Code 2007 Handbook delivers a rule-by-rule annotation of the NESC that clarifies the often confusing Code text and allows you to perform your work confidently and safely. Designed for use with the Code itself, this expert resource guides readers through safety rules for the installation, operation, and maintenance of electrical supply stations and equipment,… read more and also for overhead and underground electric supply and communication lines. read less

定价： 0元 / 折扣价： 0 元

This standard defines the interdisciplinary tasks that are required throughout a system's life cycle to transform stakeholder needs, requirements, and constraints into a system solution. This standard is intended to guide the development of systems for commercial, government, military, and space applications. The information applies to a project within an enterprise that is responsible for developing a product design and establishing the life cycle infrastructure needed to provide for life… read more cycle sustainment. This standard specifies the requirements for the systems engineering process (SEP) and its application throughout the product life cycle. It does not attempt to define the implementation of each system life cycle process, but addresses the issues associated with defining and establishing supportive life cycle processes early and continuously throughout product development. In addition, the standard does not address the many cultural or quality variables that should be considered for successful product development. The standard focuses on the engineering activities necessary to guide product development while ensuring that the product is properly designed to make it affordable to produce, own, operate, maintain, and eventually to dispose of, without undue risk to health or the environment. The requirements of this standard are applicable to new products as well as incremental enhancements to existing products. It applies to one-of-a-kind products, such as a satellite, as well as products that are massproduced for the consumer marketplace. The requirements of this standard should be selectively applied for each specific system-development project. The role of systems engineering within the enterprise environment is described in Annex A. The content of this standard describes an integrated approach to product development, which represents the total technical effort for the following: a) Understanding the environments and the related conditions in which the product may be utilized and for which the product should be designed to accommodate b) Defining product requirements in terms of functional and performance requirements, quality factors, usability, producibility, supportability, safety, and environmental impacts c) Defining the life cycle processes for manufacturing, test, distribution, support, training, and disposal, which are necessary to provide life cycle support for products read less

定价： 243元 / 折扣价： 207 元

Includes the following: 2007 NESC: This IEEE product is part of the family on NESCs. / The NESC Handbook is a powerful tool that pulls together facts, figures, and explanations that help you effectively implement the Code. Authored by Allen L. Clapp, the NESC Handbook covers NESC various requirements up to 2007, detailing important work rules and a historical perspective of the Code. / 2007 VuSpec NESC CD-ROM

定价： 0元 / 折扣价： 0 元